1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, to a stacked chip-size package (CSP) type semiconductor device.
2. Description of the Related Art
Recently, semiconductor packages have been developed to adopt stacked chip-size packages (CSPs) having substantially the same size as that of semiconductor chips.
A prior art stacked chip-size package type semiconductor device (see: JP-A-2000-307057) is constructed by a plurality of semiconductor chips stacked on a substrate. In this case, an upper one of the semiconductor chips is smaller than an lower one of the semiconductor chips. This will be explained later in detail.
In the above-described prior art stacked chip-size package type semiconductor device, however, since the largest semiconductor chip is the lowest semiconductor chip, all bonding wires connected between the semiconductor chips and the substrate are outside of the largest semiconductor chip, the substrate is much larger than the largest semiconductor chip, which would increase the stacked chip-size package in size.
It is an object of the present invention to provide a stacked chip-size package type semiconductor device capable of being decreased in size.
According to the present invention, in a semiconductor device including a substrate, a first semiconductor chip directly or indirectly on the substrate, and a second semiconductor chip located on the first semiconductor chip, the second semiconductor chip has a larger dimension than that of the first semiconductor chip.
If the second semiconductor chip is largest, the largest semiconductor chip is not the lowest semiconductor chip. As a result, some of bonding wires are inside of the largest semiconductor chip, so that the size of the substrate can be brought close to that of the largest semiconductor chip.